Semiconductor memory integrated circuits are in high demand, and the industry is always striving to improve the density of such devices. Currently, the Dynamic Random Access Memory (DRAM) is in widespread use. However, DRAM cells require a capacitor, which requires refreshing to preserve the stored data.
Accordingly, newer memory cell technologies are under consideration for the mass market. One such new memory technology is the Phase Change Random Access Memory (PCRAM). In a PCRAM, the capacitor of the DRAM cell is replaced with a phase change material, such as Germanium-Antimony-Telluride (GST) or other chalcogenide materials. An example of such a cell 30 as fabricated is shown in cross section in FIG. 1B, and is shown in schematic form in FIG. 1A. Because the structure and operation of PCRAMs are well known to those skilled in the art, they are only briefly described. The PCRAM cell is an exciting alternative to traditional capacitor-based DRAM cells because they do not require refresh and are easily scalable. (Capacitors require a given surface area to store the requisite number of charges, and hence are not easily scaled).
As shown, each PCRAM cell 30 comprises an access transistor 32 and a phase change material 34. Each access transistor 32 is selectable via a word line (row) 20, which when accessed opens a transistor channel between a bit line (column) 24 and a reference line 22. The phase change material 34 is in series between the transistor channel and the cell selection line 24, and so can be set (i.e., programmed), reset, or read via the passage of current through the material. As is well known, phase change material 34 can be set by passing a current therethrough, which modifies the material into a more conductive crystalline state. This phase change of the material 34 is reversible, and so the material 34 may be reset back to an amorphous resistive state by the passage of even a larger amount of current through the material. Such phase changing occurs in the region 34a adjacent to the bottom electrode 42b as shown in FIG. 1B. Once set or reset to make the material 34 relatively conductive (denoting storage of a logic ‘1’) or resistive (denoting storage of a logic ‘0’), the cell may be read by passing a relatively small current through the phase change material 34 and sensing the resulting voltage on the bit lines 24.
Processing of the PCRAM cell 30 uses standard semiconductor CMOS processing techniques, and does not require significant explanation to those of skill in the art. As shown in FIG. 1B, the cell 30 uses polysilicon gates for the word lines 20 as is common, and uses conductive plugs to contact the diffusion regions 44 in active portions of the silicon substrate. The phase change material 34 is sandwiched between top and bottom electrodes 42a and 42b. Contact from the bit line 24 to top electrodes 42a is established by plugs 40. Of course, conductive structures are surrounded by at least one dielectric material 35, such as silicon dioxide or silicon nitride as is well known. Pairs of adjacent cells 30 are isolated from one another using trench isolation 46, again a standard technique for isolating active structure in a silicon substrate.
Other details concerning PCRAM memory composition, operation, and fabrication can be found in the following references, all of which are incorporated by reference herein in their entireties: S. H. Lee et al., “Full Integration and Cell Characteristics for 64 Mb Nonvolatile PRAM,” 2004 Symp. on VLSI Technology Digest of Technical Papers, pps. 20-21 (2004); S. Hudgens and B. Johnson, “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,” MRS Bulletin, pps. 829-832 (November 2004); F. Yeung et al., “Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory,” Japanese Journal of Applied Physics, Vol. 44, No. 4B, pps. 2691-2695 (2005); Y. N. Hwang et al., “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24 um-CMOS Technologies,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pps. 173-147 (2003); W. Y. Cho, et al., “A 0.18-um 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM),” IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, pps. 293-300 (January 2005); and F. Bedeschi, et al., “An 8 Mb Demonstrator for High-Density 1.8V Phase-Change Memories,” 2004 Symposium on VLSI Circuits Digest of Technical Papers, pps. 442-445 (2004).
The layout of the PCRAM cells 30 in a memory array 10 is shown in a top view in FIG. 1C. The area corresponding to each cell 30 is generally demarked with a dotted-lined oval. As can be seen each reference line 22 is shared between a pair of cells 30 which also share the same bit line 24. Each of these pairs of cells 30 are contained within the same active silicon area, as shown by dotted lined box in FIG. 1C, which comprises the diffusion regions 44 and channel regions for the access transistors 32 each of the cells in the pair. Outside of these active regions, the silicon substrate comprises trench isolation 46 (see FIG. 1B), which isolates adjacent cells from one another. The minimum width ‘x’ of isolation required is dictated by layout design rules and can vary.
Laid out in this fashion, the array 10 of PCRAM cells 30 can be operated as follows. First, a cell 30 to be accessed is determined by the logic of the integrated circuitry in which the array is formed (not shown), and an appropriate word line 20 and bit line 24 are respectively activated via row decoder/driver circuitry 12 and column decoder/driver circuitry 14. The reference drivers 16 send a reference potential to each of the cells 30 in the array 10 at all times, which can be ground for example. An activated word line 20 can comprise a voltage sufficient to form a channel under the access transistors, e.g., 1.5V. The voltage to be placed on the selected bit line 24 depends on whether the accessed cell is being set or reset (collectively, “programmed”), or read. When the cell is being set, the voltage on the bit line might be approximately 2.0V, and when reset a higher voltage of perhaps 3.0V can be used. When the cell is being read, a smaller bit line 24 voltage is used (e.g., 0.5V), and the current draw through the bit line is assessed via sense amplifiers (not shown) in the column decoder/driver circuitry 14. Because such decoder/driver circuitry 12, 14, 16 is well known, it is not further discussed.
It has been discovered that the architecture of array 10 is not optimal and takes up too much space. Specifically, the layout of each cell 30 in the array of FIG. 1C has been estimated to encompass an area equivalent to 16F2, where F is the minimum lithography limit of the process used to fabricate the array 10. This is a relatively large area for a memory cell. In part, the relatively large size of the PCRAM cell is dictated by the relatively high currents (e.g., on the order of milliamps) used to set and reset the cells. Such large set and reset currents required access transistors 32 which are relatively wide, i.e., in which the active diffusion areas 44 of the silicon are ‘y’ wide as shown in FIG. 1C. Moreover, such large currents generally also require that the width of the trench isolation 46 between the cells also be relatively large (i.e., ‘x’) so as to prevent cross-talk between the cells. While such factors may naturally warrant cells designs for PCRAMs which are relatively large, the fact remains that there is room for improvement on this score. Indeed, this disclosure presents a cell design and array architecture for a PCRAM and other memories that allows for a denser array of cells.